1. Field of the Invention
The present invention relates to semiconductor devices, and more specifically, to methods of fabricating Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET).
2. Description of Related Art
Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) are widely used in semiconductor (integrated circuit) devices. Many semiconductor devices today use complementary MOSFETs (“CMOSFET”) that include N-type MOSFETs and P-type MOSFETs.
FIG. 1 through FIG. 7 are cross-sectional views for explaining a conventional method of fabricating a CMOSFET having source/drain regions with a Lightly Doped Drain (LDD) structure.
Referring to FIG. 1 through FIG. 3, a device isolation layer 15 that defines active regions is formed in a semiconductor substrate 10 having a first region and a second region. A gate insulation layer and a gate conductive layer are sequentially formed on the active region, and then patterned successively. Thus, a gate isolation pattern 20 and a gate conductive pattern 25, which are sequentially stacked on and intersect over the first region and the second region, are formed. The gate insulation layer pattern 20 and the gate conductive pattern 25 provide a gate pattern.
Then, a first mask 30 that covers the second region and exposes the first region is formed. A first low-concentration implantation 31 that uses the first mask 30 and a gate pattern exposed at the first region as an ion implantation mask is performed. Therefore, a first lightly doped region 35 is formed in the active region neighboring the gate pattern of the first region.
After removing the first mask 30, a second mask 40 that covers the first region is formed, exposing the second region. A second low-concentration implantation 41 that uses the second mask 40 and the gate pattern exposed at the second region as an ion implantation mask is performed. Thus, a second lightly doped region 45 is formed in the active region neighboring the gate pattern of the second region.
Referring to FIG. 4 through FIG. 7, after removing the second mask 40, gate spacers 50 are formed on both sidewalls of the gate pattern. The gate spacers 50 may reduce a short channel effect induced by excessive diffusion of high-concentration impurities that are implanted in a subsequent ion implantation processes. The short channel effect may result in punch-through, hot carrier effects and the like.
A third mask 60 is formed on the semiconductor substrate including the gate spacers 50 to cover the second region and expose the first region. A first ion implantation 61 that uses the third mask 60, the gate pattern exposed at the first region and the gate spacers 50 as an ion implantation mask is performed. As a result, a first heavily doped region 65 is formed in the active region neighboring the gate spacers 50 of the first region.
After removing the third mask 60, a fourth mask 70 is formed to cover the first region and expose the second region. Then, a second high-concentration implantation 71 that uses the fourth mask 70, the gate pattern exposed at the second region and the gate spacers 50 as an ion implantation mask is performed. As a result, a second heavily doped region 75 is formed in the active region neighboring the gate spacers 50 of the second region. Then, the fourth mask 70 is removed.
In the above method, most of the masks 30, 40, 60 and 70 are formed using a photolithographic process that may increase fabrication cost. Accordingly, it may be desirable that steps using a photolithographic process be decreased to reduce fabrication costs of a semiconductor product.